1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a power IC having elemental devices formed in an SOI (semiconductor on insulator) substrate.
2. Description of the Related Art
Recently, integrated circuits (ICs), each having many transistors, resistors, and the like connected to form an electric circuit and integrated into one chip, have been widely used for the important portions of computers and communication equipments. Of these ICs, an IC including a high-withstand-voltage device is called a power IC.
Elemental devices arranged in a power IC include a vertical bipolar transistor. A vertical bipolar transistor is a transistor in which, for example, a base region is selectively formed in the surface of a collector region in a semiconductor layer, and an emitter region is selectively formed in the surface of the base region, so that a main current path extends vertically. The collector, base, and emitter regions are respectively connected to electrodes through low-resistance contact layers formed in the surfaces of the respective regions. A low-resistance buried layer containing an impurity at a high concentration is formed in the lower portion of the collector region. The buried layer may or may not be directly connected to the collector contact layer.
The buried layer in the collector region decreases the resistance on the collector region side, and plays an important role in obtaining good device characteristics. However, in order to form the buried layer, several steps must be added. This contradicts the cost requirement that a plurality of devices to be arranged in a power IC should be formed in common steps to manufacture the IC in the minimum number of steps.